AK4601VQ Datasheet, PDF (46/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
1-1. Data BUS Group Delay
2*(1/fs) group delay occurs in total as audio data will have group delay of 1*(1/fs) at each input and
output port of the data bus that have the same sync domain. Therefore, this group delay will increase as
the number of times that the data go through the data path increases.
2. Clock Sync Domain Setting for Input/Output Port
Domain numbers are assigned to each Clock Sync Domain (Table 19). Each input/output port has
setting registers for Clock Sync Domain (Figure 20).
Set a domain number to clock sync domain setting registers for each input/output port. (Table 20, Table
21)
Domain Number Clock Sync Domain
0x0
Reference Clocks are Low
0x1
SD1 (BICK SD1, LRCK SD1)
0x2
SD2 (BICK SD2, LRCK SD2)
Table 19. Clock Sync Domain Number
(default)
If the output port sync domain setting is in auto mode, an audio data port inherits the sync domain of the
input data.
Clock Sync Domain of the SDINx pin is automatically selected by setting EXBCKx[2:0] bits, MSN bit and
SDBCKx[2:0] bits (Table 15, Table 16, Table 18).
e.g.)
SD2 are selected for Clock Sync Domain of the SDIN2 pin when EXBCK2[2:0] bits = “010” and MSN2 bit
=“0” (Figure 18).
Figure 18. Clock Sync Domain Setting Example1 of SDINx Pin
e.g.)
SD2 are selected for Clock Sync Domain of the SDIN1 pin when EXBCK1[2:0] bits = “001”, MSN1 bit
=“1” and SDBCK1[2:0] bits = “010” (Figure 19).
Figure 19. Clock Sync Domain Setting Example2 of SDINx Pin
016000391-E-01
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