AK4601VQ Datasheet, PDF (42/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
e.g.) Internal Dividing Clock is Selected as PLL Reference Clock
• PLL Setting
REFSEL[2:0] bits = “000” (PLL Reference Clock is MCKI pin = 3.072MHz), PLL MCLK = 122.88MHz
• Clock Sync Domain Setting
SDADC[2:0] bits = “001”, SDCODEC[2:0] bits = “002”, MSN1 bit = MSN2 bit = “1”,
CKS1[2:0] = “001” (PLL MCLK is set as the reference clock of Clock Sync Domain 1)
BDV1[8:0] = “0x0EF” (BICK SD1 = MBICK1 = 122.88MHz/240 = 0.512MHz)
SDV1[2:0] = “000” (LRCK SD1 = MLRCK1 = 0.512MHz/64 = 8kHz)
CKS2[2:0] = “001” (PLL MCLK is set as the reference clock of Clock Sync Domain 2)
BDV2[8:0] = “0x027” (BICK SD2 = MBICK2 = 122.88MHz/40 = 3.072MHz)
SDV2[2:0] = “000” (LRCK SD2 = MLRCK2 = 3.072MHz/64 = 48kHz)
• ADC1 and CODEC Setting
FSMODE[4:0] bits= “01010” (Set fs = 8kHz for ADC1, Set CODEC, fs = 48kHz)
MCKI pin=3.072MHz
PLL_MCLK=122.88MHz
PLL
BICK1 pin(64fs)
LRCK1 pin(fs=8kHz)
MBICK1(64fs)
Internal Dividing Clock ^{MLRCK1(fs=8kHz)}
BICK_SD1(64fs)
Divide
LRCK_SD1(fs=8kHz)
MSN1=”1”
DATA BUS
ADC1
SDOUT1～
ADC1
fs=8kH5z FSMODE[4:0] bits=”01010”
fs=8kHz
BICK2 pin(64fs)
LRCK2 pin(fs=48kHz)
MBICK2(64fs)
Internal Dividing Clock ^{MLRCK2(fs=48kHz)}
BICK_SD2(64fs)
Divide
LRCK_SD2(fs=48kHz)
MSN2=”1”
ADC2,M
SDOUT1～
ADC2,M
SD^DO^ACU5¹T^-31～
DAC1-3
fs=485kHz FSMODE[4:0] bits=”01010”
fs=48kHz
DATA BUS
Figure 16. ADC, DAC, Setting Example
(MSNx bit = “1”: Internal Dividing Clock is Selected as PLL Reference Clock)
016000391-E-01
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2016/12