AK4601VQ Datasheet, PDF (35/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
■ System Clock
1. Clock Mode
12. Functional Descriptions
The AK4601 has a PLL circuit to generate an internal operation clock. An input pin for the PLL reference
clock is selected by REFSEL[2:0] bits (Table 4). REFMODE[4:0] bits set the frequency of the reference
clock (Table 5). A reference clock input pin and the reference clock frequency must be changed during
clock reset.
REFSEL[2:0] bits
Reference Clock
000
MCKI pin
(default)
001
BICK1 pin
010
BICK2 pin
Others
N/A
Table 4. PLL Reference Clock Frequency Setting
REFMODE[4:0]
Input Frequency (kHz)
bits
48kHz base 44.1kHz base
00000
256
235.2
(default)
00001
384
352.8
00010
512
470.4
00011
768
705.6
00100
1,024
940.8
00101
1,152
1,058.4
00110
1,536
1,411.2
00111
2,048
1,881.6
01000
2,304
2,116.8
01001
3,072
2,822.4
01010
4,096
3,763.2
01011
4,608
4,233.6
01100
6,144
5,644.8
01101
8,192
7,526.4
01110
9,216
8,467.2
01111
12,288
11,289.6
10000
18,432
16,934.4
10001
24,576
22,579.2
Others
N/A
N/A
Table 5. Reference Clock Frequency Setting
The PLL block multiplies a input clock which is set by REFMODE[4:0] bits directly and generates a
122.88MHz/112.896MHz master clock (PLL_MCLK) for internal operation (Table 6).
Master Clock 48kHz base 44.1kHz base
(PLL_MCLK) 122.88MHz 112.896MHz
Table 6. Internal Operation Master Clock
A stable BICK is required when using clock input from BICKx (x=1~2) pin as reference clock. A clock
with two different frequencies cannot be used. The MCKI pin must be put to “L” (DVSS1) if the system
does not need the MCKI pin.
016000391-E-01
- 35 -
2016/12