AK4601VQ Datasheet, PDF (40/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
2-3. Sampling Frequency Setting of ADC, DAC Blocks
The ADC, DAC blocks of the AK4601 are operated by a master clock generated by dividing PLL MCLK.
Sampling frequencies of the ADC1, and the ADC2, ADCM, DAC1, DAC2 and DAC3 (hereinafter called
CODEC) are set by FSMODE[4:0] bits (Table 12).
Mode
FSMODE[4:0]
bits
ADC2, ADCM
DAC1, DAC2, DAC3
ADC1
0
00000
8kHz
8kHz (default)
1
00001
12kHz
12kHz
2
00010
16kHz
16kHz
3
00011
24kHz
24kHz
4
00100
32kHz
32kHz
5
00101
32kHz
16kHz
6
00110
32kHz
8kHz
7
00111
48kHz
48kHz
8
01000
48kHz
24kHz
9
01001
48kHz
16kHz
10
01010
48kHz
8kHz
11
01011
96kHz
96kHz
12
01100
96kHz
48kHz
13
01101
96kHz
32kHz
14
01110
96kHz
24kHz
15
01111
96kHz
16kHz
16
10000
96kHz
8kHz
17
10001
192kHz
192kHz
18
10010
192kHz
96kHz
19
10011
192kHz
48kHz
20
10100
192kHz
32kHz
21
10101
192kHz
16kHz
Table 12. Sampling Frequency Settings of Internal Blocks (fs=48kHz base)
Clock Sync Domain of the ADC1 (SDADC1) is selected by SDADC1[2:0] bits and Clock Sync Domain of
the CODEC (SDCODEC) is selected by SDCODEC[2:0] bits (Figure 20). SDADC1 and SDCODEC must
be synchronized with PLL MCLK. The sampling frequency of LRCK SDx for SDADC1 and the sampling
frequency of the ADC1 should be the same. The sampling frequency of LRCK SDx for SDCODEC and
the sampling frequency of the CODEC should also be the same.
Set SDADC1[2:0] bits = “000” (Reference Clocks are Low) when not using the ADC1. In the same
manner, SDCODEC[2:0] bits must be set to “000” (Reference Clocks are Low) when not using the
CODEC.
016000391-E-01
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2016/12