AK4601VQ Datasheet, PDF (41/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

e.g.) Input pin is selected for PLL Reference Clock.
• PLL Setting
REFSEL[2:0] bits = “010” (PLL Reference Clock is set to BICK2 pin=3.072MHz)
• Clock Sync Domain Setting
SDADC1[2:0] bits = “001”, SDCODEC[2:0] bits = “002”, MSN1 bit = MSN2 bit = “0”,
BICK_SD1 = BICK1 pin = 64fs (0.512MHz), LRCK_SD1 = LRCK1 pin = 8kHz
BICK_SD2 = BICK2 pin = 64fs (3.072MHz),LRCK_SD2 = LRCK2 pin = 48kHz
• ADC1 and CODEC Setting
FSMODE[4:0] bits=” 01010” (Set fs = 8kHz for ADC1, Set CODEC, fs = 48kHz)
[AK4601]
BICK2 pin=3.072MHz
PLL_MCLK=122.88MHz
PLL
BICK1 pin(64fs)
LRCK1 pin(fs=8kHz)
Internal Dividing Clock
MBICK1
MLRCK1
BICK_SD1(64fs)
Divide
LRCK_SD1(fs=8kHz)
MSN1=”0”
BICK2 pin(64fs)
LRCK2 pin(fs=48kHz)
Internal Dividing Clock
DATA BUS
ADC1
SDOUT1～
ADC1
fs=8kH5z FSMODE1[4:0] bits=”01010”
fs=8kHz
MBICK2
MLRCK2
Divide
BICK_SD2(64fs)
LRCK_SD2(fs=48kHz)
MSN2=”0”
ADC2,M
SDOUT1～
SD^DO^ACU5¹T^-31～
ADC2,M
DAC1-3
fs=48⁵kHz
FSMODE[4:0] bits=”01010”
fs=48kHz
DATA BUS
Figure 15. ADC, DAC Setting Example (MSNx bit = “0”: Input pin is selected as PLL Reference Clock)
Note 42. BICK1/LRCK1 and BICK2/LRCK2 must be synchronized.
016000391-E-01
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2016/12