AK4601VQ Datasheet, PDF (65/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
■ LDO (Internal Circuit Drive Regulator)
The AK4601 has a regulator for driving internal digital circuits (LDO). Connect a 2.2μF (±30%) capacitor
between the AVDRV pin and the DVSS2 pin. The LDO starts operation by releasing power-down mode,
and control register settings can be made 1ms after the power-down release (PDN pin=“H”).
The AK4601 has an overcurrent protection circuit to avoid abnormal heat of the device that is caused by
a short of the AVDRV pin to VSS and etc., and an overvoltage protection circuit to protect from exceeded
voltage when the voltage to the AVDRV pin gets too high. When these protection circuits perform,
internal circuits are powered down. The internal circuit will not return to a normal operation until being
reset by the PDN pin after removing the problems.
■ Power-down and Reset
1. AK4601 Power-down and Reset Statuses and Power Management
Power-down and power-down release of the AK4601 is controlled by the PDN pin. After power-down is
released, the power management and reset of the AK4601 are controlled by registers such as
CKRESETN bit (Clock Reset) and power management bits for each block.
There are two states for the AK4601 other than normal operation: Power-down and Clock Reset. The
power-down state means the status that the PDN pin is “L”. In this state, all blocks of the AK4601 stop
the operation.
The clock reset state means the status that the PDN pin is “H” and CKRESETN bit is “0”. In this state,
the ADC, DAC, blocks are not in operation because the PLL circuit and internal clocks are stopped.
State
PDN pin
Setting
CKRESETN bit
Power-down
L
x
Clock Reset
H
0
Clock Reset Release
H
1
(Note 49)
Table 30. Reset State Definitions of the AK4601 (x: Don’t Care)
Note 49. A stable clock should be supplied before releasing clock reset (CKRESETN bit = “1”).
2. Power-down
The AK4601 can be powered down by bringing the PDN pin = “L”. Output statuses of power-down mode
are shown in Table 3.
3. Power-down Release
The REF generation circuit (reference voltage source) and a power supply circuit for internal digital
circuit are powered-up by bringing the PDN pin to “H” from “L” after an interval of 600ns or more when
AVDD, LVDD, TVDD are powered up. Control register settings should be made with an interval of 1ms
or longer after setting the PDN pin = “H”.
016000391-E-01
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2016/12