AK4601VQ Datasheet, PDF (44/111 Pages) Asahi Kasei Microsystems – Audio HUB CODEC with Digital Mixer

[AK4601]
Note 43. Set MSNx bit to “0” when using the BICKx pin as PLL reference clock input pin.
When MSELN bit = “1”, the BICK2/SDIN3 pin works as SDIN3 (Input) even setting MSN2 bit to “1”, and
the LRCK2/SDOUT3 pin works as SDOUT3 (Output) even setting MSN2 bit to “0”.
MSELN bit
0
0
1
1
MSN2 bit
0
1
0
1
Function
BICK2 (Slave mode, Input)
LRCK2 (Slave mode, Input) (default)
BICK2 (Master mode, Output) LRCK2 (Master mode, Output)
SDIN3 (Input)
SDOUT3 (Output)
Table 17. BICK2/SDIN3 Pin Setting 2
When BICKx/LRCKx (x=1~2) pin is set to Slave mode, the reference clock of Clock Sync Domain x is the
BICKx/LRCKx pin (Table 7).When BICKx/LRCKx pin is set to Master mode, the output clock of the
BICKx/LRCKx pin can be selected from two Sync Domains by SDBCKx[2:0] bits (x= 1~2). (Table 18)
MSNx bit SDBCKx[2:0] bits BICKx pin/LRCKx pin
1
000
TieLow
1
001
BICK SD1, LRCK SD1
1
010
BICK SD2, LRCK SD2
1
011
1
100
1
101
N/A
1
110
1
111
0
xxx
Input
(default)
Table 18. Clock Sync Domain Setting of BICKx/LRCKx Pin
016000391-E-01
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2016/12