AK61584 Datasheet, PDF (6/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
SWITCHING CHARACTERISTICS-T1 CLOCK/DATA (TA = -40 to 85^oC;power supply
pins within +/-5% of nominal; Inputs: Logic 0=0V, logic 1=DV+)(See Figures 1,2, and 3)
Parameter
Symbol Min Typ Max Units
TCLK Frequency
(Note 25)
ftclk
- 1.544 -
MHz
TCLK Duty Cycle
tpwh2/tpw2 30
50
70
%
RCLK Duty Cycle
(Note 26) tpwh1/tpw1 45
50
55
%
Rise Time
All Digital Outputs
(Note 27)
tr
-
-
65
ns
Fall Time
All Digital Outputs
(Note 27)
tr
-
-
65
ns
TPOS/TNEG to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG Hold Time
th2
25
-
-
ns
RPOS/RNEG to RCLK Rising Setup Time
tsu1
-
274
-
ns
RCLK Rising to RPOS/RNEG Hold Time
th1
-
274
-
ns
Notes: 25. Max value of 8.192 MHz describes the maximum burst rate of a gapped input clock(TCLK).
For the gapped clock to be tolerated by the AK61584, the jitter attenuator must be switched to
transmit path of the line interface. The maximum gap size is defined in the Analog Specification table.
26. RCLK duty cycle may be outside the spec limits when jitter attenuator is in the receive path,
and when the jitter attenuator is employing the overflow/underflow protection mechanism.
27. At max load of 50pF.
SWITCHING CHARACTERISTICS-E1 CLOCK/DATA (TA = -40 to 85^oC;power supply
pins within +/-5% of nominal; Inputs: Logic 0=0V, Logic 1=DV+)(See Figures 1, 2, and 3)
Parameter
Symbol Min Typ Max Units
TCLK Frequency
(Note 25) ftclk
- 2.048 -
MHz
TCLK Duty Cycle
tpwh2/tpw2 30
50
70
%
RCLK Duty Cycle
(Note 26) tpwh1/tpw1 45
50
55
%
Rise Time
All Digital Outputs
(Note 27)
tr
-
-
65
ns
Fall Time
All Digital Outputs
(Note 27)
tr
-
-
65
ns
TOPS/TNEG to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TOPS/TNEG Hold Time
th2
25
-
-
ns
RPOS/RNEG to RCLK Rising Setup Time
tsu1
-
194
-
ns
RCLK Rising to RPOS/RNEG Hold Time
th1
-
194
-
ns
0185-E-00
-6-
‘98/04