AK61584 Datasheet, PDF (25/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
Boundary Scan Register: The BSR can be connected in ured as an input by the JTAG BSR if the device is in
parallel to all the digital I-O pins, and provides the host mode.
mechanism for applying/reading test patterns to/from
the board traces. The BSR is initialized and read Thus, the entire BSR is 62 bits long.
using the instruction SAMPLE/PRELOAD. The bit BSR Pin
PIN Pad
ordering for the BSR is the same as the top-view packaged bits Name
# Type
pin out, counter-clockwise beginning with PD1 (pin 15) 1 PD1
15 input
and ending with LOS1 (pin 7), as shown in Table 6. The 2 IPOL,RLOOP2
33 input
analog, oscillator, power, ground, ATTEN0, CLKE 3 PD2
34 input
and MODE pins are not included as part of the 4 CODER2
41 input
boundary-scan register. ATTEN0, CLKE and MODE are 5-7 LOS2
42 bi-directional
not included because they are typically hard-wired to 8-10 TNEG2,AIS2
43 bi-directional
power or ground on a board.
11 TPOS2,TDATA2 44 input
12 TCLK2
45 input
All output pins are 3-state pins (logic high, logic low or high 13-14 RNEG2,BPV2
46 output
impedance); their value can be set via the 15-16 RPOS2,RDATA2 47 output
PRELOAD/EXTEST instructions. Since outputs 17-18 RCLK2
48 output
are all 3-state, 2 bits are required to specify the states of 19 CODER1
49 input
each output pin in the BSR.The first bit (which is shifted 20 CON22
50 input
in first) contains the testing data which may be output on 21-23 CON21
51 bi-directional
the pin. The second bit, which is shifted in following the 24-26 CON12
52 bi-directional
first bit, selects between an output-enabled state (bit set to 27-29 CON11
53 bi-directional
1) or high-impedance state (bit set to 0). Thus, two 30-32 CON02
54 bi-directional
J_TCK cycles are required to load testing data for 33-35 CON01
58 bi-directional
each output pin.
36-38 TAOS2
59 bi-directional
39-41 SDI,TAOS1
60 bi-directional
Each input pin requires only 1 bit in the BSR.
42-44 SDO,LLOOP1
61 bi-directional
45 SCLK,LLOOP2 62 input
The bi-directional pins, TNEG1/AIS1, TNEG2/AIS2, 46-48 INT,RLOOP1
63 bi-directional
INT/RLOOP1, LOS1, LOS2, LLOOP1/SCLK, 49 CS,ATTEN1
64 input
LLOOP2/SDO, TAOS1/SDI, TAOS2/SPOL, and the 50-51 RCLK1
1 output
CON<0:2> pins have three bits in the BSR. The first 52-53 RPOS1,RDATA1 2 output
bit shifted into the BSR captures the value of the pin. 54-55 RNEG1,BPV1
3 output
This pin may have its value set externally (if the third bit 56 TCLK1
4 input
is 0) or set internally (if the third bit is 1). The second bit 57 TPOS1,TDATA1 5 input
shifted into the BSR sets the output value. This value is 58-60 TNEG1,AIS1
6 bi-directional
output on the pin when the third bit is 1. The third bit con- 61-63 LOS1
7 bi-directional
figures the output driver as high-impedance (bit set to Table 6 Boundary Scan Register Contents
0) or active (bit set to 1).
Bypass Register: The Bypass register consists of a single
Note that the interrupt pin on the AK61584 has the bit, and provides a serial path between J_TDI and J_TDO,
ability of being a active high or active low signal. In bypassing the BSR. The provision of this register allows
host mode, the IPOL pin controls this functionality. the bypassing of those segments of the board-level serial
During JTAG testing in host mode, the polarity of the test register which are not required for a specific test. This
INT pin will be determined by the state of the IPOL pin. also reduces test access times, by reducing the total num-
The INT pin on the AK61584 should not be configured ber of shifts required from J_TDI to J_TDO.
as an output by the JTAG BSR if the device is in hard-
ware mode. Likewise, the INT pin should not be config-
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