AK61584 Datasheet, PDF (23/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
7 (MSB) 6
BM
ADD5
0 individual
1 Burst
(MSB)
5
ADD4
Don't care
4
ADD3
3
ADD2
2
ADD1
Register Address Field
Figure 14. Address Command Byte (ACB)
1
ADD0
(LSB)
0 (LSB)
R/W
0 Write
1 Read
HOST MODE REGISTER ACCESS
This mode is selected by setting pin MODE to
logic high, and pin 16 must be set to logic low. In the host
mode, the on-board registers can be written to via
the SDI pin or read from via the SDO pin at the clock
rate determined by SCLK. Through these registers, a
host controller can be used to control operational char-
acteristics and monitor device status. The serial port
read/write timing is independent of the system transmit
and receive timing.
Any read or write to the serial port is initiated by setting
Chip Select (CS) low and writing an 8-bit ad-
dress/command byte (ACB). The ACB consists
of the three separate fields including a 6-bit register
address (see Figure 14). The ACB is followed by a
data word.
In the ACB, D0(LSB) is the R/W field, and
specifies whether the current operation is to be a read or
a write: 1 = read, 0= write. The next 4 bits (D1-D4)
contain the address field. They specify which of the
registers to access. D5 and D6 are “don’t care bits”.
Setting bit D7 to 1 selects burst mode (described
below).
Registers h10 to h17 are read and written as described
above. Registers h18 and h19 are used to access mul-
tiple bytes for the arbitrary waveform generation, refer
to the AK61584 Application Note.
Another communication option, burst mode, is
available. Burst mode is specified by setting bit
D7(MSB) of the ACB to 1. Burst mode allows
multiple registers to be consecutively read or written.
Writing all registers allows fast initialization at
power-up or system reset. When using burst mode, the
address field of the ACB command word must be h00.
The registers are read or written in address order h10 to
h11, followed by 42 byte reads or writes to register
h18, followed by 42 bytes read or writes to register
h19. Burst mode ends on the first rising edge of CS,
and may be ended at any time. If a burst write ends
before writing 92 bytes, the remaining, unwritten
bytes are unchanged.
Figure 15 shows the timing relationships for data
transfers. When the SPOL pin is high, data on SDO is
valid on the falling edge of SCLK. When the SPOL
pin is low, data on SDO is valid on the rising edge
of SCLK.
All data is written to and read from the port LSB
first. When writing to the port, SDI input data is sam-
pled on the rising edge of SCLK.
SDO goes to high impedance state when not in use.
SDO and SDI may be tied together in applications
where the host processor has a bi-directional I/O
port.
CS
SCLK
SDI
SDO
0185-E-00
R/W 0 0
0
0
1
0
Address/Command Byte
0 D0 D1 D2 D3 D4 D5 D6 D7
Data Input/Output
D0 D1 D2 D3 D4 D5 D6 D7
Figure 15. Serial Read/Write Timing
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‘98/04