AK61584 Datasheet, PDF (13/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
In 62411 applications, an overriding design considera-
tion is management of jitter. Typically, the AK61584
will use it's jitter attenuator on the receive side to re-
duce the jitter seen by the system synchronizer. The
transmit clock presented to the AK61584 by the system
will be Stratum 4 quality or better, and is input to both
the reference clock pin and transmit clock pin. If an
independent clock source is used for the reference clock,
the jitter on the reference clock must be well below the
jitter allowed by 62411.
Category I Asynchronous Multiplexer
Application
Category II Synchronous Application
A typical example of a category II application is a T1
card of a central office switch or a 0/1 digital
cross-connect system. These systems use receive side
jitter attenuation to reduce the jitter presented to the
system, and will use a Stratum 3 or better system clock
to feed the AK61584 transmit and reference clocks. In
these systems, a single hardware design can support T1
and/or E1 under software control since the rate of the
transmit/reference clock rate will be varied by the sys-
tem to match the line rate(T1 or E1).
Asynchronous multiplexers take multiple T1/E1 lines
(which are asynchronous to each other), and combine
them into a higher speed transmission rate. Examples
are M13 muxes, and SONET muxes. In these systems,
the jitter attenuator is used on the transmit side of the
AK61584 to remove the waiting time jitter caused by
the multiplexer. Because the transmit clock is jittered,
the reference clock to the AK61584 will be provided by
an external quartz crystal, which operates at the 1-X or
8-X data rate. T1/E1 framers are typically not required
in asynchronous multiplexers, so the B8ZS/
AMI/HDB3 coders in the AK61584 are activated.
TRANSMITTER
The transmitter takes data from a T1 or E1 terminal,
and produces pulses of appropriate shape. The transmit
clock (TCLK) and transmit data (TPOS & TNEG, or
TDATA) are supplied synchronously. Data is sampled
on the falling edge of the input clock.
Pulse shaping and signal level are determined by con-
figuration inputs as shown in Table 1. Typical output
pulses are shown in Figures 9 and 10.
C CC
OOO
NNN
210
000
001
010
011
100
101
110
TRANSMITTER
Pulse Width at Pulse Shape
50% amplitude
244 ns(50%)
244 ns(50%)
350 ns(54%)
350 ns(54%)
350 ns(54%)
350 ns(54%)
350 ns(54%)
E1:square, 2.37 Volts into 75ohm
E1:square, 3.00 Volts into 120ohm
DSX-1:0-133ft
DSX-1:133-266ft
DSX-1:266-399ft
DSX-1:399-533ft
DSX-1:533-655ft
CON3 must be set to 0.
Table 1. Configuration Selection
RECEIVER
Slicing
Coder
Level
50%
50%
65%
65%
65%
65%
65%
AMI/HDB3
AMI/HDB3
AMI/B8ZS
AMI/B8ZS
AMI/B8ZS
AMI/B8ZS
AMI/B8ZS
0185-E-00
-13-
‘98/04