AK61584 Datasheet, PDF (28/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
Shift-DR State
In this controller state, the test data register connected
between J_TDI and J_TDO as a result of the current in-
struction shifts data on stage toward its serial output on
each rising edge of J_TCK.
The instruction does not change in this state.
When the TAP controller is in this state and a rising
edge is applied to J_TCK, the controller enters the
Exit1-DR state if J_TMS is high or remains in the
Shift-DR state if J_TMS is low.
Exit2-DR State
This is a temporary state. While in this state, if
J_TMS is held high, a rising edge applied to J_TCK
causes the controller to enter the Update-DR state,
which terminates the scanning process. If J_TMS is
held low and a rising edge is applied to J_TCK, the
controller enters the Shift-DR state.
The test data register selected by the current instruc-
tion retains its previous value during this state. The
instruction does not change in this state.
Exit1-DR State
Updata-DR State
This is a temporary state. while in this state, if J_TMS is
held high, a rising edge applied to J_TCK causes the
controller to enter the Update-DR state, which termi-
nates the scanning process. If J_TMS is held low and a
rising edge is applied to J_TCK, the controller
enters the Pause-DR state.
The test data register selected by the current instruction re-
tains its previous value during this state. This instruction
does not change in this state.
The Boundary Scan Register is provided with a
latched parallel output to prevent changes at the parallel
output while data is shifted in response to the EXTEST
and SAMPLE/PRELOAD instructions. When the
TAP controller is in this state and the Boundary Scan
Register is selected, data is latched onto the parallel
output of this register from the shift-register path on
the falling edge of J_TCK. The data held at the
latched parallel output does not change other than in
this state.
Pause-DR State
The pause state allows the test controller to temporarily
halt the shifting of data through the test data register in the
serial path between J_TDI and J_TDO. An example
use of this state could be to allow tester to reload its pin
memory from disk during application of a long test
sequence.
The test data register selected by the current instruc-
tion retains its previous value during this state. The
instruction does not change in this state.
The controller remains in this state as long as J_TMS
is low. When J_TMS goes high and a rising edge is
applied to J_TCK, the controller moves to the Exit2-DR
state.
All shift-register stages in the test data register selected by
the current instruction retains their previous value during
this state. The instructions does not change in this state.
Select-IR-Scan State
This is a temporary controller state. The test data
register selected by the current instruction retains its
previous state. If J_TMS is held low and a rising edge
is applied to J_TCK when in this state, the controller
moves into the Capture-IR state, and a scan sequence
for the instruction register is initiated. If J_TMS is
held high and a rising edge is applied to J_TCK, the
controller moves to the Test-Logic-Reset state. The
instruction does not change in this state.
0185-E-00
-28-
‘98/04