AK61584 Datasheet, PDF (15/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
RECEIVER
is mode via control register (Channel 1 Control A, bit 7).
The receiver extracts data and clock from the T1/E1
signal and outputs clock and synchronized data. The
receiver can receive signals over the entire range of
short haul cable lengths.
The clock recovery circuit is a second-order phase
lock loop, and can tolerate as much as 0.4U1 of jitter
from 10 kHz to 100kHz, without error (Figure 11). The
clock and data recovery circuit is tolerant of long strings
of consecutive zeros, and will successfully receive a
1-in-175, jitter- free input signal.
300
100
28
10
PEAK-TO-PEAK
JITTER
(unit intervals)₁
AK61584
Performance
AT&T62411
(1990 Version)
0.4
0.1
1
10
100 300 700 1k
10k
JITTER FREQUENCY(Hz)
100k
Figure 11. Minimum Input Jitter Tolerance of Receiver
(Clock Recovery Circuit and Jitter Attenuator)
Data at RPOS and RNEG, is stable and may be
sampled using the recovered clock. CLKE determines
the clock polarity for which output data is stable and valid
as shown in Table 3. When CLKE is high, RPOS and
RNEG are valid on the falling edge of RCLK. When
CLKE is low, RPOS and RNEG are valid on the rising
edge of RCLK. In Hardware mode, the CLKE selec-
tion is made via pin 27. In host mode, the CLKE selection
CLKE DATA
LOW
HIGH
RPOS
RNEG
RPOS
RNEG
CLOCK
RCLK
RCLK
RCLK
RCLK
Clock edge for
valid data
Rising
Rising
Falling
Falling
Table 3. Data Output/Data relationship
The signal is detected differentially across the receive
transformer. Recommended receiver transformer
specifications are identical to the transmit transformer
specifications.
Receiver Loss of Signal
The receiver will indicate loss of signal upon receiv-
ing 175+/-15 consecutive zeros. A digital counter
counts received zeros, based on recovered clock cy-
cles. The receiver reports loss of signal by setting the
appropriate Loss of Signal pin, LOS high. The LOS
condition is exited using the ANSI T1.231- 1993 criteria,
namely 12.5% ones density for175+/-75 bit periods with
no more than 100 zeros in a row.
If a loss of signal condition occurs when the host mode is
being used, the LOS and LOS-latched bits will be set
and an interrupt will be issued. LOS will go low (and flag
the interrupt pin again, if the serial I/O is used) when a
valid signal is detected. The LOS-latched bit will stay high
until read, and then will remain low until the next loss
of signal event occurs. See Figure 12. Note that in the
hosts mode serial port operation, LOS is simultane-
ously available from both the register and pin LOSx.
LOS Currently Active
(LOS bit & LOS pin)
Latched LOS
(Latch LOS bit)
Interrupt
(INT)
Read LOS bits
"Short" LOS event
"Long" LOS event
Set by start of LOS
Cleared by Read
Cleared by Read
Set by Change of LOS
Figure 12 Loss of Signal Event Relationship
0185-E-00
-15-
‘98/04