AK61584 Datasheet, PDF (18/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
The non-selected channel operates normally. Selecting
PD1 or PD2 does not reset the AK61584 control reg-
isters, or serial control ports. Simultaneously selecting
PD1 and PD2 will power down some additional
analog circuitry that is shared by both channels. After
exiting the power down state, the channel will be fully
operational in less than 20 ms.
RESET
In operation, the AK61584 is continuously calibrated,
making the performance of the device independent
of power supply or temperature variations. The
continuous calibration function forgoes any requirement
to reset the line interface when in operation.
The RESET pin resets the entire device, including the
control logic, and clears all control and mask registers.
A reset event results in the Latched-reset bit being set in
the Status register. A reset request can be made by
setting RESET high for at least 200 ns. Reset will ini-
tiate on the falling edge of RESET. The reset operation
takes less than 20 ms to complete. Upon exiting
RESET, both channels are powered up.
POWER ON RESET
Upon power-up, the IC is held in a static state until the
supply crosses a threshold of approximately 60% of the
power supply voltage. When this threshold is crossed, the
device will delay for about 10 ms to allow the power
supply to reach operating voltage. After this delay, cali-
bration of the transmit and receive sections commences.
The calibration can take place only if REFCLK and
TCLK are present. The initial calibration takes less
than 20 ms. The power-on reset has the same effect as the
RESET. A power-on reset event results in the Latched-reset
bit being set in the Status register.
CONTROL
Control of the AK61584 is via either host mode (regis-
ter read/write via serial control port), or hardware mode
(individual control pin). Hardware mode offers significantly
fewer programmability options than the host mode.
The following pins are used to select the mode. The
MODE pin active low selects Hardware mode. The
MODE pin active high enables host mode. Once host
mode is invoked, the pin 16 must be set to logic low. The
definition of the pins in each mode is shown in the
block diagram of the first page of the data sheet.
Hardware Mode
The following control options are available in Hard-
ware mode on a per channel basis: power down, remote
loopback, transmit all ones, coder mode, line length
selection and location of jitter attenuator.
Host Modes
Host mode allows a microcontroller to read/write ten
AK61584 control and status registers. The registers
are defined in Table 5, and discussed in a later section.
Host mode interface ports are available for serial.
In host mode, the AK61584 registers occupies a
six-bit address space, where those six bits select a
register in the range h10 to h19.
The AK61584 generates an interrupt on pin INT
whenever a status register changes. The polarity of the
INT pin is programmable. When the IPOL pin is high,
INT goes high to generate a processor interrupt.
When the IPOL pin is low, INT goes low to generate
a processor interrupt.
0185-E-00
-18-
‘98/04