AK61584 Datasheet, PDF (1/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
AK61584
Dual Low Power T1/E1 Line Interface
Features
- Provides Dual Analog PCM Line Interface
for short-haul,T1 and E1 applications
- Jitter Tolerance: Compliant with AT&T62411
TR-NWT-000499 Category I,II ITU-T G.823
- Transmitter Pulse Shape: Compliant with
AT&T62411,CB119, TR-NWT-000499,
ITU-T G.703
- Jitter Transfer: AT&T62411, ITU-T G.736
- Operating mode fully software configurable.
No external quartz crystal is required.
- Support of JTAG boundary scan
- Low Power Consumption
- 3.3Volt operation
- Small Plastic Package 64pin LQFP(10*10*
1.4mm)
General Description
The AK61584 is a universal line interface for T1/E1 applica-
tions, designed for high-volume cards where low power,
high density and universal operation is required. One board
design can support all T1/E1 modes.
The AK61584 is a low-power CMOS device available
in 3.3 Volt.
Serial Port IPOL (Note) CS INT SCLK SDO SDI SPOL
Hardware mode RLOOP2 ATTEN0 ATTEN1 RLOOP1 LLOOP1 LLOOP2 TAOS1 TAOS2 CON01 CON02 CON11 CON12 CON21 CON22 CODER1 CODER2 CLKE
CONTROL
TCLK1
(TDATA1)TPOS1
(AIS1)TNEG1
RCLK1
(RDATA1)RPOS1
(BPV1)RNEG1
JITTER
ATTENUATOR
TAOS
PULSE
SHAPING
CIRCUITRY
DRIVER
LOS&
AIS
DETECT
CLOCK&
DATA
RECOVERY
TTIP1
TRING1
RTIP1
RRING1
TCLK2
(TDATA2)TPOS2
(AIS2)TNEG2
RCLK2
(RDATA2)RPOS2
(BPV2)RNEG2
JITTER
ATTENUATOR
TAOS
PULSE
SHAPING
CIRCUITRY
DRIVER
LOS&
AIS
DETECT
CLOCK&
DATA
RECOVERY
TTIP2
TRING2
RTIP2
RRING2
JTAG CLOCK GENERATOR
4
2
2
2
2
3
CONTROL
RESET
MODE
REFCLK 1XCLK TV+ TGND RV+ RGND DV+ DGND AV+ AGND BGREF PD1 PD2 LOS1 LOS2
Note) In host mode, this pin must be tied to GND.
Preliminary Product Information
This document contains information for a new product. AKM
reserves the right to modify this product without notice.
0185-E-00
-1-
‘98/04