AK61584 Datasheet, PDF (20/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
Register
Address
h10
b0010
h11
b0011
Bit Name
Channel 1 Mask
Definition
Reset
1
0
Value
7 Mask LOS1 Mask status bit 7
6 Mask Latched- Mask status bit 6
LOS1
5 Mask AIS1 Mask status bit 5
4 Mask Latched- Mask status bit 4
AIS1
3 Mask Latched- Mask status bit 3
BPV1
2 Mask Latched Mask status bit 2
-Overflow1
1 reserved
0 Mask
Mask status bit 0 &
Interrupt1
Interrupt pin
Channel 2 Mask
Enable status bit 7
0
Enable status bit 6
0
Enable status bit 5
0
Enable status bit 4
0
Enable status bit 3
0
Enable status bit 2
0
0
Enable status bit 0 & 0
Interrupt pin
7 Mask LOS2 Mask status bit 7
6 Mask Latched- Mask status bit 6
LOS2
5 Mask AIS2 Mask status bit 5
4 Mask Latched- Mask status bit 4
AIS2
3 Mask Latched- Mask status bit 3
BPV2
2 Mask Latched Mask status bit 2
-Overflow2
1 reserved
0 Mask
Mask status bit 0 &
Interrupt2
Interrupt pin
Enable status bit 7
0
Enable status bit 6
0
Enable status bit 5
0
Enable status bit 4
0
Enable status bit 3
0
Enable status bit 2
0
0
Enable status bit 0 & 0
Interrupt pin
Note)Mask LOS and Mask Latched-LOS need to controlled simultaneously, and Mask AIS and Mask
Latched-AIS also.
Table 5(b). Mask Registers
Mask Registers Description
Writing a “1” to a bit of the mask register forces the corre-
sponding bit of the status register to stay fixed at “0”.
AMI-T: Writing a “0” enables the B8ZS or HDB3
encoder in the transmit path. B8ZS vs. HDB3 se-
lection is determined by the CON<0:2> bits. Writing
a “1” enables the AMI encoder.
Control A Registers Description
Each bit in the control register is defined below.
AMI-R: Writing a “0”enables the B8ZS or HDB3
decoder in the receiver path. B8ZS vs. HDB3 se-
lection is determined by the CON<0:2> bits. Writing
a “1” enables the AMI decoder.
CLKE: When CLKE is set to “1”. RPOS and
RNEG are valid on the falling edge of RCLK.
When CLKE is set to “0”, RPOS and RNEG are
valid on the rising edge of RCLK. This bit con-
trols the RPOS/RNEG polarity for both host
modes. The CLKE pin provides the same function-
ality for the hardware mode.
0185-E-00
-20-
‘98/04