AK61584 Datasheet, PDF (26/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
JTAG Instructions and Instruction Register
(IR)
The instruction register (2 bits) allows the instruction
to be shifted into the circuit. The instruction is
used to select the test to be performed or the data
register to be accessed or both. The valid instructions
are (LSB shifted in first):
IR CODE
00
01
11
INSTRUCTION
EXTEST
SAMPLE/PRELOAD
BYPASS
EXTEST Instruction: The EXTEST instruction
allows testing of off-chip circuitry and board-level
interconnect. EXTEST connects the BSR to J_TDI
and J_TDO. The normal path between the
AK61584 logic and it's IO pins is broken; the sig-
nals on the output pins are loaded from the BSR; the
signals on the input pins are loaded into the BSR.
SAMPLE/PRELOAD
Instruction:
The
SAMPLE/PRE-LOAD instructions allows scanning of
the boundary-scan register without interfering with the
operation of the AK61584. This instruction connects
the BSR to J_TDI and J_TDO. The normal path be-
tween the AK61584 logic and its IO pins is main-
tained; the signals on those IO pins is maintained; the
signals on those 10 pins are loaded into the BSR. Addi-
tionally, this instruction can be used to latch values
into the digital output pins.
BYPASS Instruction: The BYPASS instruction
connects the minimum length, Bypass register
between J_TDI and J_TDO, and allows data to
be shifted in the shift-DR controller state.
Internal Testing Considerations
Note that the INTEST instruction is not supported be-
cause of the difficulty of performing significant internal
tests using JTAG. The most complete internal test
would involve inputting digital data on pins TCLK,
TPOS, TNEG, activating local loopback#2, and
reading that same data out on pins RCLK, RPOS
and RNEG. This test would include the full
transmit path, the full receive path, and optionally, the
jitter attenuator, and provides excellent test coverage of
the functional blocks. However, this test is diffi-
cult to implement for two reasons.
First, TCLK and REFCLK must be clocked at specific
frequencies, e.g., T1/E1+/-200 ppm for TCLK. If
these frequency requirements are not met, the per-
formance of the transmitter, clock recovery circuit
and jitter attenuator is not guaranteed. If would be
difficult with JTAG to toggle the TCLK input at the
required rate.
Second, the loopback path includes two asynchronous
blocks, clock recovery and jitter attenuator. Therefore,
the exact time delay for a TPOS-input appearing on
RPOS-output is variable, making output signature
correlation difficult.
The one test that could be easily performed using an ar-
bitrary clock rate on TCLK and REFCLK is local
loopback#1, with jitter attenuator disabled. However,
that test provides such limited fault coverage, that is
only useful in determining if the device had been
catastrophically destroyed. Alternatively, catastrophic
destrucion of the IC and/or surrounding board traces
can be detected using EXTEST. Therefore, the IN-
TEST instruction was viewed as providing little
significant incremental testing capability, while ad-
ding to product complexity, and was not included in
the AK61584.
JTAG TAP Controller
Figure 20 shows the state diagram for the TAP state
machine. A description of each state follows. Note
that the figure contains two main branches to access
either the data or instruction registers. The value
shown next to each state transition in this figure is
the value present at J_TMS at each rising edge of
J_TCK.
0185-E-00
-26-
‘98/04