AK61584 Datasheet, PDF (34/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
Power Supplies
AGND-Ground, Analog, Pin 23.
Analog supply ground pin.
AV+ -Power Supply, Analog, Pin 24
Analog supply ground pin for internal bandgap reference, oscillator and internal clock
multipliers
BGREF-Bandgap Reference, Pin 22
Used by the internal bandgap reference. This pin should be connected to ground by a 5k
ohm resister
DGND1, DGND2, DGND3 -Ground, Pins 57, 9, 55.
Power supply ground pin for the digital circuitry in both channels.
DV+ -Power Supply, Pin 56
Power supply pin for the digital circuitry in both channels.; typically +3.3 Volts referenced
to DGND.
RGND1, RGND2 -Ground, Receiver, Pins 20, 29.
Power supply ground pins for the receivers.
RV+1, RV+2 -Power Supply, Receiver, Pins 19, 30.
Power supply pins for the analog circuitry in the receivers; typically +3.3 Volts referenced
to RGND1 and RGND2.
TGND1, TGND2 -Ground, Transmit Drivers, Pin 13, 36
Power supply ground pins for the transmitters.
TV+1, TV+2 -Power Supply, Transmit Drivers, Pins 12, 37.
Power supply pins for the transmitter analog circuitry; typically +3.3 Volts references
to TGND1 and TGND2.
Control Pins and Control Buses
ATTEN0 ATTEN1 -Jitter Attenuator Select, Pin 16, 64. (Hardware Mode)
selects, for both channels, which path has jitter attenuation (transmit/receive/neither).
See Table 4. In host mode, pin 16 must be tied to GND.
CLKE -Clock Edge, Pin 27. (Hardware mode)
CLKE controls RCLK polarity. Setting CLKE to logic 1 causes RPOS and RNEG (RDATA) to be
valid on the falling edge of RCLK. Conversely, setting CLKE to logic 0 causes RPOS and RNEG
(RDATA) to be valid on the rising edge of RCLK.
CODER1,CODER2-Coder enable, Pins 49, 41. (Hardware mode)
Setting CODER to logic 1 enables a coder (B8ZS or HDB3),setting CODER to logic 0 transparent
mode enables.
0185-E-00
-34-
‘98/04