AK61584 Datasheet, PDF (36/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
SCLK -Serial Clock, Pin 62. (Host mode)
Clock used to read or write the serial port registers. SCLK can be either high or low when
the line interface is selected using the CS pin.
SDI -Serial Data Input, Pin 60. (Host mode)
Data for the on-chip register. Sampled on the rising edge of SCLK.
SDO -Serial Data Output, Pin 61. (Host mode)
Status and control information from the on-chip register. If SPOL is high SDO is valid
on the rising edge of SCLK. If SPOL is low, SDO is valid on the falling edge of SCLK. This
pin goes to a high-impedance state when the serial port is being written to or after bit
D7 is output.
TAOS1,2 -Transmit All Ones Select, Pin 60, 59. (Hardware Mode)
Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined
by REFCLK.
Status
AIS1, AIS2 -All Ones Signal Detection, Pins 6, 43.
AIS goes high when an all-ones condition is detected using the detection criteria of less
than nine zeros out of 8192 bit periods.
BPV1, BPV2 -Bipolar Violation Detection, Pins 3, 46.
BPV goes to a logic 1 for one bit period when a bipolar violation is detected in the
received signal. B8ZS (or HDB3) zero substitutions are not flagged as bipolar violations
if the B8ZS (or HDB3) decoder has been enabled.
LOS1, LOS2 -Loss of Signal, Pins 7, 42.
LOS goes to a logic 1 when 175 consecutive zeros have been detected. LOS returns to logic 0
when a 12.5% ones density signal returns.
SPOL -SDO Polarity Control, Pin 59. (Host mode)
setting SPOL to logic 1, causes SDO to be valid on the rising edge of SCLK. Setting SPOL to
logic 0 causes SDO to be valid on the falling edge of SCLK.
Reference Clock
1XCLK -One-times Clock Frequency Select, Pin 28.
When 1XCLK is set to logic 1, REFCLK should be a 1.544 MHz for T1 or 2.048 MHz for E1
applications. When 1XCLK is set to logic 0, REFCLK should be an 8x clock, i.e., 12.352 MHz
for T1 or 16.384 MHz for E1 applications.
REFCLK -External Reference Clock Input, Pin 26.
A reference clock for the receiver and jitter attenuator circuits of both channels. When
1XCLK is set to logic 1, REFCLK should be 1.544 MHz for T1 or 2.048 MHz for E1 applications.
When 1XCLK is set to logic 0, REFCLK should be 12.352 MHz for T1 or 16.384 MHz for E1
applications.
0185-E-00
-36-
‘98/04