AK61584 Datasheet, PDF (24/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
Arbitrary Waveform Registers
These registers are written multiple times to enter an
arbitrary waveform.
tion of the de-coupling capacitors. A 5kohm, 1%,
resistor should connect BGREF to ground.
JTAG BOUNDARY SCAN
ARBITRARY WAVEFORM GENERATION
In additon to the predefined pulse shapes, the user can
create arbitrary pulse shapes using the host mode for
evaluation. Refer to the AK61584 Application Note.
POWER SUPPLY
The device operates from a single 3.3 Volt supply.
Separate pins for the various supplies provide internal
isolation. However, these pins should be connected ex-
ternally with the power supply pins de-coupled to their
respective grounds. The various ground pins must not be
more negative than AGND.
De-coupling and filtering of the power supplies is cru-
cial for the proper operation of the analog circuits. The
best way to configure the power supplies is to tie all
of the supply pins together at the chip. As shown in
Figure 1, a capacitor should be connected between
each supply and its respective ground. For the 1uF and
smaller capacitors, use mylar or ceramic capacitors and
place them as closely as possible to their respective
power supply pins. Wire-wrap bread boarding of
the line interface is not recommended because lead
resistance and inductance serve to defeat the func-
JTAG boundary scan supports board testing. Using
boundary scan, the integrity of the digital paths between
ICs on a board can be verified. This verification
is supported by the ability to externally set the
signals on the AK61584's digital output pins, and to
externally read the signals present on the AK61584's
input pins.
As shown in Figure 16, the JTAG hardware consists of
data and instruction registers plus a Test Access
Port (TAP) controller. Control of the TAP is achieved
through signals applied to the Test Mode Select
(J_TMS) and Test Clock (J_TCK) input pins. Data is
shifted into the registers via the Test Data Input
(J_TDI) pin, and shifted out of the registers via the Test
Data Output (J_TDO) pin, again using J_TCK. The
Instruction register defines which data register is
included in the shift operation. Note that if J_TDI
is left floating, an internal pull-up resistor forces
the pin high.
JTAG Data Registers (DR)
The test data registers are: the Boundary-Scan
Regiser (BSR), and the Bypass Register (BR).
Digital output pins Digital input pins
Parallel latched
output
JTAG Block
J-TDI
J-TCK
J-TMS
Boundary Scan Data Register
32bit Data Register(Factory use only)
Bypass Data Register
Instruction(shift) Register
Parallel latched
output
TAP Controller
MUX
J-TDO
0185-E-00
Figure 16. JTAG Circuitry Block Diagram
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‘98/04