AK61584 Datasheet, PDF (29/38 Pages) Asahi Kasei Microsystems – Dual Low Power T1/E1 Line Interface

ASAHI KASEI
[AK61584]
Capture-IR State
In this controller state, the shift register contained in the
instruction register loads a fixed value of “01” on the ris-
ing edge of J_TCK. this supports fault-isolation of the
board-level serial
test data path.
Data registers selected by the current instruction retain
their value during this state. The instruction does not
change in this state.
When the controller is in this state and a rising edge is ap-
plied to J_TCK, the controller enters the Exit1-IR state if
J_TMS is held high, or the Shift-IR state if J_TMS is
held low.
Shift-IR State
In this state the shift register contained in the instruction
register is connected between J_TDI and J_TDO and
shifts data one stage towards its serial output on each
rising edge of J_TCK.
The test data register selected by the current instruc-
tion retains its previous value during this state. The
instruction does not change in this state.
When the controller is in this state and a rising edge is ap-
plied to J_TCK, the controller enters the Exit1-IR state
if J_TMS is held high, or re-mains in the Shift-IR state if
J_TMS is held low.
Exit1-IR State
This is a temporary state. while in this state, if J_TMS
is held high, a rising edge applied to J_TCK causes the
controller to enter the Update-IR state, which termi-
nates the scanning process. If J_TMS is held low and a
rising edge is applied to J_TCK, the controller enters the
Pause-IR state.
Pause-IR State
The pause state allow the test controller to tempo-
rarily halt the shifting of data through the instruction
register.
The test data register selected by the current instruc-
tion retains its previous value during this state. The in-
struction does not change in this state.
The controller remains in this state as long as J_TMS is
low. When J_TMS goes high and a rising edge is ap-
plied to J_TCK, the controller moves to the Exit2-IR
state.
Exit2-IR State
This is a temporary state. While in this state, if J_TMS
is held high, a rising edge applied to J_TCK causes the
controller to enter the Update-IR state, which termi-
nates the scanning process. If J_TMS is held low and a
rising edge is applied to J_TCK, the controller enters the
Shift-IR state.
The test data register selected by the current instruc-
tion retains its previous value during this state. The
instruction does not change in this state.
Updata-IR State
The instruction shifted into the instruction register
is latched onto the parallel output from the
shift-register path on the falling edge of J_TCK. Once
the new instruction has been latched, it becomes the cur-
rent instruction.
Test data registers selected by the current instruction
retain their previous value.
JTAG Application Examples
The test data register selected by the current instruc-
tion retains its previous value during this state. The
instruction does not change in this state.
Figures 18 and 19 show examples of updating the in-
struction register and data registers.
0185-E-00
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‘98/04