AK7746 Datasheet, PDF (56/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
[AK7746]
b) SO data read (during run phase)
SO outputs data on DBUS (data bus) of the DSP section. Data is set when @MICR the DST field specifies. Setting of data
allows DRDY to go to "H", and data is output synchronized with the falling edge of SCLK. When SI goes to "H", DRDY goes to "L"
to wait for the next command. Once DRDY goes to "H", the data of the last @MICR command immediately before DRDY goes to "H"
will be held until SI goes to "H" or read out 24-bit data with SCLK, and subsequent commands will be rejected. A maximum of 24 bits
are output from SO.
Note) In the case of read out 24-bit data, DRDY falls down when 24^th SCLK rising edge and SO output bit is not stable. So, if the
microcontroller cannot read out at SCLK rising edge, it should ignore the last 1bit (D0).
S_RESET
RQ
SI
@MICR
DRDY
SCLK
SO
Data1
24 SCLK Clock
D23 D22 D21* * * * * D3 D2 D1 D0
Data2
Less than 24 SCLK
D23 D22 D21D20 D19 D18
Fig.8-31 SO read (during RUN phase)
[MS0369-E00]
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2004/12