AK7746 Datasheet, PDF (40/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
[AK7746]
(6) Audio data interface (internal connection mode)
The serial audio data pins SDIN1,SDIN2,SDIN3,SDIN4,SDOUT1,SDOUT2,SDOUT3, SDOUT4, SDOUTA1 and SDOUTA2 are
interfaced with the external system, using LRCLK_I, LRCLK_O, BITCLK_I and BITCLK_O. These ports are controlled via registers.
( See the block diagram on page.2 and the control register setting section at page 28.)
The data format is MSB-first 2's complement. Normally, the input/output format, in addition to the standard format used by AKM,
can be changed to I²S compatible mode by setting the control register “CONT0 DIF (D4) to 1”. (In this case, all input/output audio data
pin interface are in the I²S compatible mode.)
The input SDIN1, SDIN2, SDIN3 and SDIN4 formats are MSB justified 24-bit at initialization. Setting the control registers
CONT0: DIF1 (D3), DIF0 (D2) will cause these ports to be compatible with LSB justified 24-bit, 20-bit and 16-bit.
However, individual setting of SDIN1, SDIN2, SDIN3 and SDIN4 is not allowed. The output SDOUT1, SDOUT2,
SDOUT3 and SDOUT4 are fixed at 24-bit MSB justified only. The ADCM is monoral but outputs same data for Lch and Rch.
In slave mode BITCLK_I corresponds to not only 64fs but also 48fs. 64fs is the recommended mode. Following formats
describe 64fs examples.
1) Standard input format (DIFS = 0: default set value)
a) Mode 1 (DIF[1:0] = 0 default set value)
LRCLK
Left ch
Right ch
BITCLK
31 30 29
10 9 8 7 6 5 4 3 2 1 0 31 30 29
10 9 8 7 6 5 4 3 2 1 0
SDIN1,SDIN2,
SDIN3,SDIN4
M 22 21
21L
M 22 21
21L
M : MSB, L : LSB
Fig.8-10
* When you want to input the MSB-justified 20-bit data into SDIN, SDINA input four "0" following the LSB.
b) Mode 2, Mode 3, Mode 4
SDIN1,SDIN2,SDIN3,SDIN4
SDIN1,SDIN2,SDIN3,SDIN4
SDIN1,SDIN2,SDIN3,SDIN4
Mode2 : DIF[1:0]=1 LSB justified 24-bit
Mode3 : DIF[1:0]=2 LSB justified 20-bit
Mode4 : DIF[1:0]=3 LSB justified 16-bit
LRCLK
BITCLK
SDIN1,SDIN2,
SDIN3,SDIN4
SDIN1,SDIN2
SDIN3,SDIN4
SDIN1,SDIN2
SDIN3,SDIN4
Left ch
Right ch
31 30
23 22 21 20 19 18 17 16 15 1 0 31 30
23 22 21 20 19 18 17 16 15 ^{1 0}
Don't Care M 22 21 20 19 18 17 16 15 1 L Don't Care M 22 21 20 19 18 17 16 15 1 L
Don't Care
M 18 17 16 15 1 L Don't Care
M 18 17 16 15 1 L
Don't Care
M 1 L Don't Care
M 1L
M : MSB, L : LSB
Fig.8-11
[MS0369-E00]
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2004/12