AK7746 Datasheet, PDF (55/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
[AK7746]
4) Read-out during RUN phase (SO output )
a) Control register data read (during run phase)
The control register can read during run time. To read data written into the control registers, input the command code and 16
bits of SCLK. After the input command code, the data of D7 to D1 outputs from SO is synchronized with the falling edge of SCLK. D0
is invalid, so please ignore this bit.
Data transfer procedure
c Command code 70h,72h,74h,76h,78h,7Ah, 7Ch, 7Eh
In order to know the each bit function, see 8. Function description (2) Control registers.
S_RESET =”H”
RQ
SCLK
SI
SO
70h (example)
D7 **** D1
74h (example)
D7 **** D1
Fig.8-30 Control register read (during RUN phase)
[MS0369-E00]
- 55 -
2004/12