AK7746 Datasheet, PDF (13/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
(5) Switching Characteristics
5-1) System clock
(AVDD=DVDD=3.0V~3.6V,Ta=-40~85°C)
Parameter
Master clock (XTI)
a) With a crystal oscillator:
CKS[1:0]=0h
Note 1)
CKS[1:0]=1h
b) With an external clock:
Duty factor (≤18.5MHz)
(>18.5MHz)
CKS[1:0]=0h
Note 1)
CKS[1:0]=1h
CKS[1:0]=2h @SMODE=”L”
(BITCLK_I input )
CKS[1:0]=2h @SMODE=”H”
(PLL enable frequency)
Clock rise time
Clock fall time
LRCLK Sampling Frequency
Slave mode :clock rise time
Slave mode :clock fall time
Symbol
fMCLK
fMCLK
fMCLK
fMCLK
fXTI
fXTI
tCR
tCF
fs
tLR
tLF
min
-
-
40
45
16.0
11.0
―――
2.75
8
typ
16.9344
18.432
11.2896
12.288
50
50
48
BITCLK_I, BITCLK Frequency
(@CKS[1:0]≠ 2h)
Note 3)
fBCLK
48
Slave mode: High level width
Slave mode: Low level width
tBCLKH
70
tBCLKL
70
Slave mode :clock rise time
tBR
Slave mode :clock fall time
tBF
BITCLK_I, BITCLK Frequency Note 4)
―
64
(@CKS[1:0]=2h, SMODE=”L”)
fBCLK
2.75
(PLL enable frequency )
Duty
40
50
Slave mode: High level width
Slave mode: Low level width
tBCLKH
140
tBCLKL
140
Slave mode :clock rise time
tBR
Slave mode :clock fall time
tBF
Note 1) CKS[1]=CKS1, CKS[0]=CKS0
Note 2) LRCLK and sampling rate (fs) must be matched.
Note 3) 48fs is enabled in slave mode.
Note 4) When using BITCLK_I as master clock. Accurate 64 divide clock is required during 1fs.
(Available fs are 44.1kHz and 48kHz ).
5-2) Reset
(AVDD=DVDD=3.0V~3.6V,Ta=-40~85°C)
Parameter
Symbol
min
typ
INIT_RESET
Note 1) ^tRST
600
S_RESET
tRST
600
Note 1) When “H”, the AK7746 needs a stable master clock input to the device.
[AK7746]
max
Unit
-
-
60
55
18.6
12.4
―――
3.1
6
6
96
8
8
64
6
6
―
3.1
60
6
6
MHz
MHz
%
%
MHz
MHz
MHz
MHz
ns
ns
kHz
ns
ns
fs
ns
ns
ns
ns
fs
MHz
%
ns
ns
ns
ns
max
Unit
ns
ns
[MS0369-E00]
- 13 -
2004/12