AK7746 Datasheet, PDF (22/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
[AK7746]
8. Function Description
(1) Various Settings
1-1) SMODE: slave and master mode selector pin
This pin sets LRCLK and BITCLK to either inputs or outputs.
a) Slave mode: SMODE="L"
LRCLK_I (1fs) and BITCLK_I (64fs or 48fs) are inputs.
The LRCLK_O outputs the input signal to LRCLK_I.
The BITCLK_O outputs the input signal to BITCLK_I.
Note) BITCLK_I is able to input 48fs when CKS[1:0]≠2h.
b) Master mode: SMODE=”H”
LRCLK_I and BITCLK_I is disabled.
LRCLK_O outputs 1fs, BITCLK_O outputs 64fs.
Note) SMODE pin can be chenged while the S_RESET is ”L”. (When stopping XTI or changing the frequency, it must be set
during the initial reset ( INIT_RESET =”L” and S_RESET =”L”).
When the input frequency is changed, it should be done during the initial reset ( INIT_RESET =”L” and S_RESET =”L”).
1-2) CKS1 pin,CKS0 pin: Master Clock (XTI or BITCLK_I) select pin
CLK
Mode
CKS
[1:0]
SMODE
Clock
Input pin
0
0h “L”,”H”
XTI
1
1h “L”,”H”
XTI
2S
2h
“L”
BITCLK_I
2M
2h
“H”
XTI
3
3h “L”,”H”
N/A
Note) CKS1=CKS[1], CKS0=CKS[0]
Main Input
frequency
(MHz)
18.432, 16.9344
12.288, 11.2896
3.072, 2.8224
3.072, 2.8224
N/A
Available
Frequency
Range
(MHz)
16.0~18.6
11.0~12.4
2.75~3.1
2.75~3.1
N/A
Crystal
use
OK
OK
NG
NG
N/A
Internal
PLL
Use
Use
Use
Use
N/A
CLK Mode 2S is available only when fs =44.1kHz and 48kHz. CLK Mode 3 is not available (test use only).
The internal master clock (MCLK) of the AK7746 is 36.864MHz maximum.
Maximum
number of
DSP Steps
(fs=48kHz)
768
768
768
768
N/A
CLK Mode 0
XTI
1/6
18.432MHz/16.9344MHz
PLL × 12
MCLK
36.864MHz/33.8688MHz
CLK Mode 1
XTI
1/4
12.288MHz/11.2896MHz
PLL × 12
MCLK
36.864MHz/33.8688MHz
CLK Mode 2S
BITCLK_I
3.072MHz/2.8224MHz
PLL × 12
MCLK
36.864MHz/33.8688MHz
CLK Mode 2M
XTI
3.072MHz/2.8224MHz
PLL × 12
MCLK
36.864MHz/33.8688MHz
Fig.8-1 Relationship of XTI or BITCLK_I and MCLK (internal master clock)
[MS0369-E00]
- 22 -
2004/12