AK7746 Datasheet, PDF (35/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
(4) Resetting
[AK7746]
The AK7746 has two reset pins: INIT_RESET and S_RESET .
The INIT_RESET pin is used to set up VREF and initialize the AK7746, as shown in "Power supply startup sequence section (3)."
The system is reset when S_RESET =”L”. (Description of "reset" is for "system reset".)
During a system reset, a program write operation is normally performed (except for write operation during running).
During the system reset phase, the ADC sections are also reset. (The digital section of ADC output is MSB first 00000h).
However, VREF will be active; LRCLK and BITCLK in the master mode will be inactive.
The system reset is released by setting S_RESET to "H", which activates the internal counter.
This counter generates LRCLK and BITCLK in the master mode: however, a problem may occur when a clock signal is
generated.
When the system reset is released in slave mode, internal timing will be actuated in synchronization with rising edge "Ç" of
LRCLK (when the standard input format is used). Timing between the external and internal clocks is adjusted at this time. Therefore
make sure to avoid phase difference between LRCLK and internal timing. If the phase difference in LRCLK and internal timing is
within about -1/16 to 1/16 of the input sampling cycle (1/fs) during the operation, the operation is performed with internal timing
remaining unchanged. If the phase difference exceeds the above range, the phase is adjusted by synchronizing the "Ç" of LRCLK
(when the standard input format is used). This prevents synchronization failure with the external circuit.
The ADC section can output 516-LRCLK after its internal counter has started. (The internal counter starts at the first rising
edge of LRCLK in master mode. In slave mode, it starts 6 LRCLKs(max) after the release of system reset. )
The AK7746 performs normal operation when S_RESET is set to "H".
♦ RAM Clear
The AK7746 will write automatically all 0 data into all DRAM and DLRAM after release the system reset. ( RAM Clear).
It takes 5*LRCLK(max)+2048*MCLK(internal master clock) at slave mode, and it takes 2*LRCLK(max)+2048*MCLK at master
mode.
Therefore in the slave mode, it will take about 160µs [(5/48kHz)+(2048/36.864MHz)] at fs=48kHz, or 174µs
[(5/44.1kHz)+(2048/33.8688MHz)] at fs=44.1kHz.
INIT_RESET
S_RESET
RAM CLEAR
DSP START
Master Mode: 1LRCLK
Slave Mode : 4LRCLK
RAM CLEAR TIME
(1LRCLK + 2048 * MCLK )
Fig.8-7 RAM CLEAR SEQUENCE
DSP PROGRAM
START
[MS0369-E00]
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2004/12