AK7746 Datasheet, PDF (32/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
[AK7746]
7) CONT6 : CLKO setting & Internal path setting ( See. 3 Block diagram)
Recommend this register changing at system reset state ( S_RESET =”L” ).
Command
Code
WR
6Ch 7Ch
Name
CONT6
D7
TEST
D6
CLKS[1]
D5
CLKS[0]
D4
SWQ4
D3
SWQ3
D2
SWQ2
D1
SWQ1
D0 Default
× 0000 000X
c D7 : TEST
0: Normal operation
1: TEST Mode ( Do NOT use. )
d D6,D5 : CLKS[1],CLKS[0] CLKO Output select
CLKS
Mode
CLKS[1] CLKS[0]
CLKO
MCLK
@36.864MHz
MCLK
@33.8688MHz
0
0
1
0
2
1
3
1
0
MCLK/2
1
MCLK/3
0
MCLK × 2/9
1
SETCK
18.432MHz
12.288MHz
8.192MHz
CONT0(D1)
16.9344MHz
11.2896MHz
7.5264MHz
CONT0(D1)
Note1) MCLK is the internal master clock. MCLK is changed by inputting XTI frequency. Normally, MCLK is 36.864MHz or
33.8688MHz. See (5) 1) Master clock select table.
Note 2) CLKS Mode 3 output data is determined by CONT0 SETCK(D1).
Note 3) It takes 12ms(max) until the clock comes out following INIT_RESET release.
Note 4) When this control register changes, noise may occur on CLKO. Once CLKO comes out, it can not stop
unless CLKE_N is set to 1 or a reset is initialized (while the clock is supplied)
e D4 : SWQ4 SDOUT4 Output select
0: Normal operation
1: Through outputs of SDIN4.
Note that it includes output delay.
f D3 : SWQ3 SDOUT3 Output select
0: Normal operation
1: Through outputs of SDIN3.
Note that it includes output delay.
g D2 : SWQ2 SDOUT2 Output select
0: Normal operation
1: Through outputs of SDIN2.
Note that it includes output delay.
h D1 : SWQ1 SDOUT1 Output select
0: Normal operation
1: Through outputs of SDIN1.
Note that it includes output delay.
i D0 : Always input 0
Note) Underlines of the c~h mean default setting.
[MS0369-E00]
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2004/12