AK7746 Datasheet, PDF (43/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
[AK7746]
1) Write during reset phase
a) Control register write (during reset phase)
The data comprises a set of 2 bytes used to perform control register write operations (during reset phase). When all data has been
entered, the new data is sent at the rising edge of the 16^th count of SCLK.
Data transfer procedure
c Command code 60h,62h,64h,66h,68h,6Ah,6Ch
d Control data
(D7 D6 D5 D4 D3 D2 D1 D0)
For the function of each bit, see the description of Control registers (p.25).
S_RESET
RQ
SCLK
SI
SO
60h
D7 ***D1 D0
64h
D7 ***D1 D0
Fig .8-15 Control Registers write operation
[MS0369-E00]
- 43 -
2004/12