AK7746 Datasheet, PDF (24/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
[AK7746]
b) BITCLK_I Select
The CLK mode 2S is used when the BITCLK_I is used instead of XTI. When selecting this mode, set SMODE=”L”.
The clock supplied on the BITCLK_I pin is directly frequency- multiplied by the PLL and a master clock is
generated. When the system is using this mode only, it is recommended to connect the XTI pin to DVSS.
XTI
0
Divider
1
XTO
External ^BITCLK_I
Clock
SMODE="L"
CKS1="H"
CKS0="L"
PLL
MCLK
BITCLK
AK7746
Fig.8-4 Image of the internal connection of the CLK mode 2S.
Input on BITCLK_I pin a divided-by-64 clock of the LRCLK_I ( 64fs ). (BITCLK_I must be in synchronized with
LRCLK_I. )
LRCLK_I
B ITC LK _I
Left ch
R ight ch
32 x BITC LK_I(BITC LK)
32 x B ITC LK _I(B ITC LK)
F ig.8-5 R elationship betw een B IT C LK _I and LR C L K _I.
[MS0369-E00]
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2004/12