AK7746 Datasheet, PDF (54/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
[AK7746]
c) External conditional jump code rewrite (during RUN phase)
Two data bytes are used to write an external conditional jump code. Data can be input during both the reset and operation
phases, and input data is set to the specified register at the rising edge of LRCLK. When all data has been transferred, the RDY pin goes
to "L". Upon completion of writing, it goes to "H". A jump command will be executed if there is any one agreement between each bit
of the 8-bit external condition code and "1"of each bit of the IFCON field. A write operation from the microcomputer is disabled until
RDY goes to "H".
Note: The LRCLK phase is inverted in the I²S-compatible state.
Data transfer procedure
c Command code C4h ( 1 1 0 0 0 1 0 0 )
d Code data
(D7 . . . . . D0)
S_RESET
SCLK
SI
SO
RQ
LRCLK
RDY
11000100 D7 *** D0
L ch R ch
max 2LRCLK
max0.25LRCLK
Fig.8-29 External condition jump write timing (during RUN phase)
[MS0369-E00]
- 54 -
2004/12