AK7746 Datasheet, PDF (39/62 Pages) Asahi Kasei Microsystems – Audio DSP with 5-channel 24-bit ADC and Input Mux

[ASAHI KASEI]
[AK7746]
2) Master Clock (XTI pin or BITCLK_I pin )
The master clock can get from the crystal oscillator connected between the XTI and the XTO pins, or from the external clock to the
XTI pin and XTO pin is open. Only the CLK mode 2S (CKS[1:0]=2h and SMODE=”L”) can use the clock input to the BITCLK_I pin
instead of the XTI pin. At that time the XTI pin should be connected to DVSS.
3) Slave Mode
When the mode is CKS[1:0]≠2h, the requied system clocks are XTI , LRCLK_I(1fs) and BITCLK_I (64fs or 48fs ). At that time, the
master clock (XTI) must be synchronized with LRCLK_I, but it does not need to be in phase.
When the mode is CKS[1:0]=2h, the requied system clocks are LRCLK_I(1fs) and BITCLK_I (64fs only, 48fs can not be use). In
this mode the master clock (BITCLK_I ) must be in synchronized with LRCLK_I and also need to be in phase.
LRCLK_I, BITCLK_I are directly output on LRCLK_O and BITCLK_O respectively.
CD etc.
XTI
(Master Equipment)
LRCLK_I
BITCLK_I
SMODE
LRCLK_O
BITCLK_O
DAC etc.
(Slave Equipment)
CLKO
Clk Gen.
1fs
64fs
CLKO
AK7746
Fig. 8-9 Slave mode example
4) Master Mode
Master mode requires a clock input to XTI pin. When a clock is applied to the XTI input, LRCLK_O and BITCLK_O are
automatically generated by an XTI-synchronized internal counter. No output is available on LRCLK_O and BITCLK_O pins during
an initial reset ( INIT_RESET ="L") and a system reset ( INIT_RESET =”H” and S_RESET ="L").
When using only for the master mode on the AK7746, the LRCLK_I and the BITCLK_I should set “L”.
[MS0369-E00]
- 39 -
2004/12