AK5406 Datasheet, PDF (5/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
38 TEST
29 COAST
24 CLAMP
DI Test pin.
Connect to AVSS. This pin has an on-chip pull-down
resistor.
DI Clock control coast input.
Upon application of this Coast input, PLL stops to
synchronize with Horizontal SYNC signal and starts to
self-run the oscillation.
It is also possible to use internally generated timing from
VSYNC, without using this pin. Connect to AVSS when
not used.
DI External Clamp input.
Input pin to select timing in order to clamp Video input to
an internal, pre-set value.
26 TEST2
DI Test pin.
Connect to PVDD through MOS SW internally.
Decoupling capacitor etc. connection pins
58 BYPASS AO Bypass capacitor connection pin for Reference Voltage.
Connect a 0.1uF capacitor between this pin and AVSS.
37 BIAS
AO Bias Current pin for internal Analog circuit.
Connect a 6.8kΩ ±1% resistor between this pin and AVSS.
33 FLT
AO External Filter connection pin for PLL.
This pin is internally fixed to PVDD at power-down mode.
Power Supply pins
39 42 AVDD
45 46
51 52
59
11 DVDD
23 67
78
27 PVDD
34 35
25 28 AVSS
32 36
40 41
44 47
50 53
60
10,22 DVSS
66,79
NC Pins
PWR Analog power supply pins.
PWR Digital power supply pins.
PWR Power supply pins for PLL.
PWR Analog ground pins.
PWR Digital ground pins.
8,9, NC
NC NC pins. Left open.
20,21
76,77
AI : Analog Input pin, AO : Analog Output pin
DI : Digital Input pin,
DO : Digital Output pin,
Ground pin
DI pins be free from Hi-Z input.
DO pins set to be Hi-Z output state by register setting.
PWR : Power Supply /
MS0592-E-01
5
2008/07