AK5406 Datasheet, PDF (2/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
■ Functional Block Description
Table 1 : Block Description
block
Function
CLAMP To Clamp Pedestal level of input signal during Clamp period.
PGA
Programmable Gain Amplifier.
It has 8-bit resolution. Full-scale input range of ADC can be
pre-set from 0.5V to 1V.
ADC
10-bit 80 MSPS AD Converter.
BLACK LOOP A loop to settle Pedestal level to the Black set value.
Can be disable by register setting.
VREF
To generate internal reference voltage.
Control Serial I/F Control register with I²C Interface (400KHz).
Sync Processing To generate timing signals such as ADC operating clock, from
Horizontal / Vertical SYNC signal inputs.
SLICER
Comparator to slice SYNC signal part in
SYNC-ON-Green signal.
PLL
PLL to generate Pixel Clock from Horizontal SYNC
signal
COAST
GEN
To generate Coast signal from VSYNC.
CLAMP
GEN
To generate Clamp signal from HSYNC.
CLP
COAST
To execute Coast processing on Clamp signal.
SYNC SEP To separate VSYNC from Slicer output.
CLAMP
CLAMP GEN
CLAMP SEL
1
0
To CLP
CLP COAST
SOGIN
HSYNC
COAST
VSYNC
SLICER
COAST GEN
1
0
COASTGEN
1
0
SOGOUT SEL
HSYNC SEL
1
0
1
0
COAST
1
0
HSYNC SEL
PLL
Sync
Separator
1
0
VSYNC SEL
Fig. 2 Sync Processing
SOGOUT
HSYNCO
DTCLK
VSYNCO
MS0592-E-01
2
2008/07