AK5406 Datasheet, PDF (31/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
Sub Address 24H
[6] COASTGEN SEL
COASTGEN SEL
COASTGEN input setting
0
VSYNC pin
1
Sync Separator output
(note) when COASTGEN SEL is set to “1”, please select the Sync Separator signal for
VSYNC SEL at Sub Address 0EH bit “0”.
[5] CLPBW
CLP BW
0
1
Clamp input / output
current
600uA
150uA
Clamp bandwidth
Standard
SLOW
[4:3] “1” is written to each of these 2 bits.
[2] SOGOUT POL
SOGOUT POL
Signal polarity to be output on
SOGOUT pin
0
Non-inverted
1
Inverted
(note) Polarity of the selected signal by SOGOUT SEL register is altered when it is
output on SOGOUT pin.
[1] SOGOUT SEL
SOGOUT SEL
0
1
Signal to be output on SOGOUT pin
SOG SLICER output
Input signal on HSYNC pin
[0] DOFIX
DOFIX
Output level at power-down
0
Fixed low
1
Fixed high
(note) Compatible pins : ROUT7-0, GOUT7-0, BOUT7-0, , HSYNCO, VSYNCO,
SOGOUT, DTCLK.
MS0592-E-01
31
2008/07