AK5406 Datasheet, PDF (32/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
Sub Address 25H LOOP DISABLE
When this register value(m) is set to value other than “0”, it is possible to divide the
clamp period into two half, where the First half is Clamp circuit operational (m pixels
clock) and Black Loop operation in the other half. (refer to timing chart 5)
When set this register value, the value must be smaller than CLP DURATION value.
Sub Address 26H PRE CLPCOAST
Default : 00H
Sub Address 27H POST CLPCOAST
Default : 00H
Parameters to coast Clamp signal are set.
In the PRE COAST register, # of preceding HSYNC periods to be coasted after VSYNC
signal, is set in the POST CLPCOAST register, # of succeeding HSYNC periods to be
coasted after VSYNC signal, is set. (refer to timing chart 6)
Sub Address 28H
[7:6] DATA DRIVE
DATA DRIVE
00
01
10
11
ROUT, GOUT, BOUT, HSYNCO,
VSYNCO, SOGOUT pin drivability
Hi-Z
Hi-Z
MAX x 1/4
MAX
[5:4] CLOCK DRIVE
CLOCK DRIVE
00
01
10
11
DTCLK pin drivability
Hi-Z
Hi-Z
MAX x 1/4
MAX
Sub Address 29H
[3:1] IN RANGE
IN RANGE
000
001
010
011
100
101
110
111
Accelerate range control of black loop setting
No acceleration
Non-boosted bandwidth when it settles within ±0.25 LSB
Non-boosted bandwidth when it settles within ±0.5 LSB
Non-boosted bandwidth when it settles within ±0.75 LSB
Non-boosted bandwidth when it settles within ±1 LSB
Non-boosted bandwidth when it settles within ± 2 LSB
Non-boosted bandwidth when it settles within ±3 LSB
Non-boosted bandwidth when it settles within ±4 LSB
Sub Address 2AH [6:0] Reserve 1 Default : 39H
Sub Address 2BH [3:0] Reserve 1 Default : 00H Reserved.
MS0592-E-01
32
2008/07