AK5406 Datasheet, PDF (4/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
■ Pin Functions
Table 2 : Pin Functions
Pin name I/O
Output Pins
64 HSYNCO DO
62 VSYNCO DO
63 SOGOUT DO
Serial Interface (I²C) Pins
57 SDA
DI/
DO
56 SCL
DI
55 AO
DI
61 RESETN DI
Data Pins
68
ROUT7
DO
~75 ~ROUT0
80, GOUT7
1~7 ~GOUT0
12
BOUT7
~19 ~BOUT0
Data Clock Pins
65 DTCLK
DO
Input Pins
54 RIN
AI
48 GIN
43 BIN
30 HSYNC
DI
31 VSYNC
DI
Functions
Horizontal SYNC output.
HSYNC output which is re-configured HSYNC input signal
by internal timing.
It is phase-synchronized with DTCLK. When phase of
DTCLK is modified by Clock Phase Adjust register setting,
this output phase also changes in sync with it.
Vertical SYNC output.
Either VSYNC input or Sync Separator could be output.
Sync-On-Green Slice comparator output.
Data I/O pins
Clock
Address
Register initialization signal input ( active low ).
RED channel ADC outputs
GREEN channel ADC outputs
BLUE channels ADC outputs
Bit 7 is the MSB. They are output in sync with DTCLK.
When DTCLK phase is modify by Clock Adjust register
setting, these output phases also change in sync with it.
Strobe clock for Data and HSYNCO. It is generated by PLL
and synchronized with internal ADC sampling clock.
Its phase changes in accordance with Clock Phase Adjust
register setting. It is phase-synchronized with HSYNCO and
Data.
RED channel analog input.
GREEN channel analog input.
BLUE channel analog input.
0.5V~1.0V full scale input. Each input signal is AC-coupled
to each pin and clamp operation is executed.
Horizontal SYNC input.
Reference Clock input to generate DTCLK clock by the
on-chip PLL (it is also possible to input Sync-On-Green
signal on SOGIN pin as Reference Clock).
Active polarity of input signal is selectable by register
setting.
Leading edge is used for this and trailing edge is ignored.
Vertical SYNC input.
49 SOGIN
MS0592-E-01
AI Sync-On-Green input.
Comparator input pin to extract SYNC signal from
Sync-On-Green signal.
Comparator threshold level is adjustable by register
setting (10 ~ 320mV / step).
When this pin is not used, connect to AVDD directly or
connect to AVSS via a 1nF capacitor.
4
2008/07