AK5406 Datasheet, PDF (19/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
5) CLAMP Timing 2
When register (LOOP DISABLE) is set to value (m) other than 0, the clamp period is
divided into 2 half where it is possible that the Clamp Circuit operational at First half
of the period (m pixels clock) and Black Loop at the other half.
When m = 0 (reset value), the Clamp Circuit and the Black Loop are operate at the
same timing.
CLAMP
(internal)
ADCLK
(internal)
1
2
m-2
m-1
m
Clamp Circuit operation
register (LOOP DISABLE) set value
Block Loop operation
Fig. 18 Clamp Timing (#2)
6) COAST Timing for Clamp
VSYNC
Reference register address
26H : PRE CLPCOAST
27H : POST CLPCOAST
HSYNC
(CSYNC)
COAST
(internal)
m
m-1
321
123
n
register（PRE-CLPCOAST）set value(m)
register（POST-CLPCOAST）set value(n)
CLAMP COAST Period
Fig. 19 Clamp Coast Timing
(note) Since PRE CLPCOAST time is counted, based on # of lines in the previous Field,
there is a case in the interlaced signal mode that COAST period may slightly differ
between Odd Field and Even Field case.
For details, refer to (3) COAST Timing section.
MS0592-E-01
19
2008/07