AK5406 Datasheet, PDF (18/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
when COAST pin is used
input signal fed on COAST pin is used as is, as internal coast signal.
normal leading edge without coast
leading edge to be coasted
HSYNC
COAST
Fig. 15 COAST Timing ( when COAST pin is used )
4) Clamp Timing 1
when CLAMP pin is not used
trailing edge
HSYNC
Reference register address
0FH : CLAMP SEL, CLAMP POL
05H : CLP PLACE
06H : CLP DURATION
ADCLK
(internal)
CLAMP
(internal)
Register (CLP PLACE) set value (m)
Register (CLP DURATION) set value (n)
Fig. 16 Clamp Timing
when CLAMP pin is used
Externally feds clamp timing pulse from CLAMP pin.
Clamp timing pulse be sampled by ADCLK then used internally.
CLAMP
ADCLK
(internal)
Internal CLAMP
Fig. 17 Clamp Timing
MS0592-E-01
18
2008/07