AK5406 Datasheet, PDF (25/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
Sub Address 04H PHADJ
[7:3]
ADC sampling clock phase
00H
-180°
01H
-168.75°
advances
:
:
↑
0EH
-22.5°
0FH
-11.25°
10H
standard
11H
+11.25°
12H
+22.5°
:
:
↓
1EH
+157.5°
delayed
1FH
+168.75°
Each single step is equal to 11.25 degrees.
A larger number reflects direction of a bigger delay.
Sub Address 05H CLP PLACE
Default : 80H
Sub Address 06H CLP DURATION
Default : 80H
Clamp timing can be internally generated when CLAMP SEL is set to “0”.
The periods of clamping is start from trailing edge of HSYNC after the delayed of CLP
PLACE pixels and its continue according to the setting of CLP DURATION pixels
value. (refer to timing chart 4)
Do not set CLP DURATION to “0” when CLP PLACE is set to “0”,”1”,”2” value.
Sub Address 07H HSYNCO WIDTH
Default : 20H
This is to set the pulse width of Horizontal SYNC signal which is re-configured by PLL
and is output on HSYNCO pin ( refer to timing charts 1 & 2 ).
Do not write this register value to “0”.
Sub Address 08H ~ 0AH RED (GREEN,BLUE) GAIN
[7:0]
Input range
Gain
[Vpp]
00H
0.377
01H
0.380
High gain
02H
0.383
↑
:
:
7FH
0.751
80H
0.754
81H
:
FDH
0.757
:
1.123
↓
Low gain
FEH
1.126
FFH
1.129
(note) PGA Gain is shown by 543/(128 + N) where (N = 0 ~ 255(DEC)).
PGA Gain is set until ADC input range becomes 1.6Vpp.
MS0592-E-01
25
2008/07