AK5406 Datasheet, PDF (27/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
Sub Address 0FH
[7] CLAMP SEL
[7]
0
1
[6] CLAMP POL
[6]
0
1
[5] COAST SEL
[5]
0
1
[3] COAST POL
[3]
0
1
[1] PDN
[1]
0
1
[AK5406]
Clamp signal to be used at CLP
Internally generated signal from
HSYNC
CLAMP pin
CLAMP input pin polarity
Active high
Active low
Signal to be used as PLL COAST
COAST pin
Internally generated signal from
VSYNC
COAST input pin polarity
Active low
Active high
Power-down control
Power-down
Normal operation
Operating functional blocks
VREF
Sync-On-Green SLICER
Total circuit
Sub Address 10H
[7:3] SOGTH
[7:3]
00H
01H
:
1EH
1FH
Default : 17H
SOG SLICER threshold level
(upward direction from SOG clamp level)
320mV
310mV
:
20mV
10mV
[2:0] RED(GREEN,BLUE)
0
1
CLP
LVL
Input clamp level
Minimum level
Center level
MS0592-E-01
27
2008/07