AK5406 Datasheet, PDF (12/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
Functional Description
ADC
10-bit 80 MSPS A/D Converter, output is reduced to 8-bit.
Reset Operation
Reset Operation must be executed after the power-up.
Reset pulse can be fed in asynchronous fashion, with a pulse width of longer than 1 us.
Right after the reset operation, registers are set to their default.
PLL Function
The Pixel Clock is re-produced by PLL based on HSYNC to be input.
The AK5406 is corresponds from 9MHz to 80MHz of frequency by adjusting Charged
Pump Current as PLL parameter.
The example of Charged Pump current calculation is shown below, and the closest value
is setting to register (Address 0x03 bit 5:3).
AK5406 PLL Cpcurrent (CPI) calculation :
CPI = ((2pi*fH)/NFRatio)^2*C*N*P / Kvco;
fH : PLL reference signal (Horizontal SYNC signalin [Hz] )
NFRatio : Set to each natural frequency
Reference signal is divided and set to 13.
C: 0.082uF
N: PLL divide ratio (Register Address 0x01, 0x02)
P: 4:<9-32MHz>, 2:<32-64MHz>, 1:<64-80MHz> Clock Frequency range.
Kvco: 130MHz
PLL Coast Funtion
The Pixel Clock is re-produced by PLL based on HSYNC to be input.
Coast mode is to cease its PLL tracking operation and to let VCO self-run.
There are 2 modes in Coast function –
One is HSYNC Pulse Duration Coast where the duration time is selected from
Pre-VSYNC timing as start point and Post-VSYNC timing as stop point, and the other is
to input directly on Coast pin a signal to notify its timing.
( refer to timing diagram 3 ) Coast Timing )
Clamp Function
This is a function to adjust reference level of AC-coupled input signal to match with the
AK5406 internal reference level. It is required to specify a specific period where
reference level of input signal is being input. It is selectable to specify the period by
external CLAMP pin or by register setting. If the clamp period is specified by register,
the position and the period from the trailing edge of HSYNC are set to the register.
( refer to timing diagram 4 ) Clamp Timing #1)
During the clamp period the Analog Clamp circuit (Clamp Block) and the Black Loop
circuit (Black Loop block) are operational at the same timing at the default setting. It is
possible to set the Analog Clamp at the first half of clamp period and Black Loop at the
other half during the clamp period by register setting. ((refer to timing diagram 5)
Clamp timing #2) Clamp function can be coasted as in the case of PLL (( refer to timing
diagram 6) Clamp Coast).
It is also possible by register setting to clamp the minimum value in accordance with
RGB signals or to clamp the center value in accordance with YUV signals (refer to
register address 10H).
Gain Adjust Function
ADC Full-Scale Input Range is adjustable within 0.5V ~ 1V by PGA (Programmable
Gain Amplifier). PGA has an 8-bit resolution.
SYNC Separation Function
MS0592-E-01
12
2008/07