AK5406 Datasheet, PDF (26/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
Sub Address 0EH
[6] HSYNC POL
[6]
0
1
HSYNC input pin polarity
Active low
( leading edge to fall )
Active high
( leading edge to rise )
[5] HSYNCO POL
[5]
0
1
HSYNCO output pin polarity
Active high
( leading edge to rise )
Active low
( leading edge to fall )
[3] HSYNC SEL
[3]
0
1
HSYNC signal to be input to
PLL
HSYNC pin
Sync-On-Green SLICER
output
Signal to be input to Sync
Separator
HSYNC pin
Sync-On-Green SLICER output
[2] VSYNC POL
[2]
0
1
VSYNCO output pin polarity
Inverted VSYNC
Normal VSYNC
[0] VSYNC SEL
[0]
VSYNC select
0
VSYNC
1
Sync Separator signal
(note) Sync Separator circuit is in power down, when bit 1 of PDN register at Sub
Address 0FH is “0”.
MS0592-E-01
26
2008/07