AK5406 Datasheet, PDF (16/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
Timing Charts
1) Output Timing
HSYNC
leading edge
R(GB)IN
PX0
PX1 PX2
(ADCLK)
[AK5406]
Reference register address
07H : (HSYNCO WIDTH)
0EH : HSYNC POL, HSYNCO POL
pipe-line delay (12 clocks )
DTCLK
R(G,B)OUT
D0
D1
D2
D3
HSYNCO
2 clocks
register set value (HSYNCO width) -1
Fig. 10 Output Timing
2) 4 : 2 : 2 Output Mode Timing
HSYNC
R(GB)IN
leading edge
PX0
PX1
PX2
pipe-line register ( 12 clocks )
(ADCLK)
DTCLK
GOUT
Y0
Y1
Y2
ROUT
U0
V1
U2
HSYNCO
Fig. 11
2 clocks
U/V alternative output
register set value ( HSYNCO width ) -1
4 : 2 : 2 Output Mode Timing
Reference register address
15H : Output Format
MS0592-E-01
16
2008/07