AK5406 Datasheet, PDF (28/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
Sub Address 11H
[7:0]
FFH
FEH
:
20H
:
01H
00H
SSEPTH
Sync Separator threshold level
Wider pulse width
↑
Standard
↓
Narrower pulse width
Sub Address 12H PRE COAST
Sub Address 13H POST COAST
Parameters in order to internally generate PLL COAST signal from VSYNC are set.
It is valid only when the COAST SEL bit is “1”.
In the PRE-COAST register, # of preceding HSYNC periods to be coasted prior to
VSYNC signal, is set and in the POST COAST register, # of succeeding HSYNC
periods to be coasted after VSYNC signal, is set (refer to timing chart 3).
Sub Address 15H
[1] OUTFORMAT
[4]
0
1
Output Format
4:2:2
4:4:4
Input & Output signals vs Channel relation is listed in the following table when 4:2:2
output format is selected ( refer to timing chart 1 & 2 ).
Channel
Red
Green
Blue
Input signal
V
Y
U
Output signal
U/V
Y
Hi-Z
MS0592-E-01
28
2008/07