AK5406 Datasheet, PDF (17/37 Pages) Asahi Kasei Microsystems – 80MSPS Triple ADC for Displays

ASAHI KASEI
[AK5406]
3) Coast Timing
when COAST pin is not used
VSYNC
Reference register address
0FH : COAST SEL, COAST POL
12H : PRE COAST
13H : POST COAST
HSYNC
(CSYNC)
COAST
(internal)
8 pixels clock period
m m-1 m-2
321
123
n-2 n-1 n
8 pixels clock period
register (PRE-COST) set value (m)
register (POST-COAST) set value (n)
COAST period
Fig. 13 COAST Timing
(note) Since PRE-COAST time is counted, based on # of lines in the previous Field,
there is a case in the interlaced signal mode that COAST period may slightly differ
between Odd Field case and Even Field case.
*525i Mode COAST example
[Field 1]
Line No.
524 525
1
2
3
4
5
6
7
8
9
10
11
12
VSYNC
HSYNC
(CSYNC)
257
line # retained
(internal)
COAST
(internal)
258
259 260 261 262 263 264
265
265-6=259
123456
7
8
264
[Field 2]
Line No. 261
262
263
264
265
266
267
268
269
270
271
272
273
274
VSYNC
HSYNC
(CSYNC)
line # retained
(internal)
258
259 260 261 262 263 264 265
264
12345
6
7
8
265
COAST
(internal)
264-6=258
equivalent pulse period
vertical sync period
equivalent pulse period
（in case of register pre-coast = 6, register post-coast = 5）
Fig. 14 COAST Timing ( 525i Mode Coast example )
MS0592-E-01
17
2008/07