AK4128A Datasheet, PDF (42/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

[AK4128A]
■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Reset & Mute
SMUTE4 SMUTE3 SMUTE2 SMUTE1 0
BYPS
0
RSTN
01H
De-emphasis
DEM41 DEM40 DEM31 DEM30 DEM21 DEM20 DEM11 DEM10
02H Input Audio Data Format 1 0 IDIF22 IDIF21 IDIF20 0 IDIF12 IDIF11 IDIF10
03H Input Audio Data Format 2 0 IDIF42 IDIF41 IDIF40 0 IDIF32 IDIF31 IDIF30
Note 39. All register values are initialized by the PDN pin = “L”.
Note 40. Writing to the address 00H ~ 03H are inhabited. The addresses defined as 0 must contain “0” data. BYPS bit and
IDIF12-10, 22-20, 32-30, 42-40 bits should be written when RSTN bit = “0”.
Note 41. I²C access becomes valid after 1.4ms (max) from PDN pin “↑”.
■ Register Definitions
Addr
00H
Register Name
Reset & Mute
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
SMUTE4 SMUTE3 SMUTE2 SMUTE1
0
BYPS 0 RSTN
R/W
R/W
R/W
R/W
RD R/W RD R/W
0
0
0
0
0
0
0
1
RSTN: Digital Reset Control
0: Reset
1: Reset Release (default)
When this bit is set to “0”, some digital blocks of the AK4128A are powered-down. In this case SRC1-4
can not operate. Control register settings are not initialized because I²C serial control interface and
control register blocks are not powered-down. Control register writings are available. The internal
oscillator for the clocks, the regulator and the reference voltage generation circuit are not powered-down.
BYPS: Bypass Mode Control
0: SRC Mode (default)
1: SRC Bypass Mode
Refer to Table 3.
SMUTE1: SRC1 Soft Mute Control
0: Soft Mute Release (default)
1: Soft Mute
In serial control mode (SPB pin= “H”), the SMUTE pin setting is ignored. SRC1 reflects the SMUTE1
bit setting.
SMUTE2: SRC2 Soft Mute Control
0: Soft Mute Release (default)
1: Soft Mute
In serial control mode (SPB pin= “H”), the SMUTE pin setting is ignored. SRC2 reflects the SMUTE2
bit setting.
SMUTE3: SRC3 Soft Mute Control
0: Soft Mute Release (default)
1: Soft Mute
In serial control mode (SPB pin= “H”), the SMUTE pin setting is ignored. SRC3 reflects the SMUTE3
bit setting.
MS1242-E-00
- 42 -
2010/09