AK4128A Datasheet, PDF (14/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

[AK4128A]
Output PORT (TDM256 slave mode)
OBICK Period
tBCK
81
ns
OBICK Pulse Width Low
tBCKL
32
ns
Pulse Width High
OLRCK Edge to OBICK “↑”
OBICK “↑” to OLRCK Edge
OBICK “↓” to SDTO1
tBCKH
32
(Note 17) tLRB
20
(Note 17) tBLR
20
tBSD
ns
ns
ns
20
ns
Output PORT (Stereo Master mode)
OBICK Frequency
fBCK
64 FSO
Hz
OBICK Duty
dBCK
50
%
OBICK “↓” to OLRCK Edge
tMBLR
−20
20
ns
OBICK “↓” to SDTO1-4
tBSD
−20
20
ns
Output PORT (TDM256 master mode)
OBICK Frequency
fBCK
-
256 FSO
-
Hz
OBICK Duty
dBCK
-
50(Note 19)
-
%
OBICK “↓” to OLRCK Edge
tMBLR
−10
-
10
ns
OBICK “↓” to SDTO1
tBSD
−20
20
ns
Reset Timing
PDN Pulse Width
(Note 18)
tPD
150
ns
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. The AK4128A can be reset by bringing the PDN pin = “L”.
Note 19. When OMCLK=512FSO. If the OMCLK=256FSO, OMCLK clock is though and output from the OBICK pin.
When OMCLK = 384FSO, dBCK= (tCLKH)/(tCLKH+1/fCLK) x100 [%] or (tCLKL)/(tCLKL+1/fCLK) x100
[%]. When OMCLK=768FSO, dBCK= (1/fCLK)/(3/fCLK) x100 [%].
OMCLK=384FSO
tCLKH
1/fCLK
OMCLK pin
tCLKH
OBICK pin Ouput
(TDM256
Master mode)
tCLKL
1/fCLK
1/fCLK
tCLKL
tCLKL
1/fCLK
OMCLK=768FSO
OMCLK pin
1/fCLK 1/fCLK 1/fCLK
1/fCLK
OBICK pin Output
(TDM256
Master mode)
3/fCLK
3/fCLK
MS1242-E-00
- 14 -
2010/09