AK4128A Datasheet, PDF (34/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

[AK4128A]
Case 2: System Reset without clock inputs
External clocks
(Input port)
(No Clock)
SDTI
(Don’t care)
External clocks
(Output port)
(Don’t care)
PDN
I nt ernal Ci rc uit
(Internal state) Power-down _{Power-up Time}
ILRCK1-4
Input wait
SDTO4
“0” data
SDTO3
SDTO2
SDTO1
UNLOCK
“0” data
“0” data
“0” data
Input Clocks
Input Data
Output Clocks
Don’t care
Don’t care
Don’t care
21ms(max)
(2)
Normal
o per ation
Power-down
Normal data “0” data
Normal data
Normal data
Normal data
“0” data
“0” data
“0” data
Figure 35. System Reset 2
Note 27. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD0 pin must be changed when the PDN
pin= “L”.
Note 28. The UNLOCK pin outputs “H” when the PDN pin= “L”. SRC data is output from SDTO1-4 pins, which
corresponds to the each sampling frequency ratio detected SRC, after a rising edge “↑” of PDN if the internal
regulator is in normal operation. In 8-channel mode, the UNLOCK pin outputs “L” when sampling frequency
ratio detection is completed at all SRC’s. The UNLOCK pin keeps outputting “H” if there is one SRC which does
not finished sampling frequency ratio detection.
Note 29. (1) is the total time of “Internal circuit power-up + FSO/FSI ratio detection + Clock detection + Internal circuit
group delay”.
Note 30. (2) is the total time of “FSO/FSI ratio detection + Clock detection + Internal circuit group delay”.
MS1242-E-00
- 34 -
2010/09