AK4128A Datasheet, PDF (41/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

[AK4128A]
3. READ Operations
Set R/W bit = “1” for the READ operation of the AK4128A.
After transmission of the data, the master can read next address’s data by generating an acknowledge instead of terminating
the write cycle after the receipt of the first data word. After the receipt of each data, the internal address counter is
incremented by one, and the next data is taken into next address automatically. If the address exceeds 03H prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The AK4128A supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
3-1. CURRENT ADDRESS READ
The AK4128A contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would
access data from the address “n+1”.
After receipt of the slave address with R/W bit set to “1”, the AK4128A generates an acknowledge, transmits 1byte data
which address is set by the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generate the stop condition, the AK4128A discontinues transmission.
SD A
S
T
A
R
S la ve
A ddr ess
T
Data(n)
Data(n+1)
Data(n+2)
S
Data(n+x)
T
O
P
S
P
A
A
A
A
C
C
C
C
K
K
K
K
Figure 46. CURRENT ADDRESS READ
3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with
the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues a start condition, slave address (R/W=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to
“1”. Then the AK4128A generates an acknowledge, 1byte data and increments the internal address counter by one. If the
master does not generate an acknowledge but generate the stop condition, the AK4128A discontinues transmission.
SD A
S
T
A
R
S la ve
A ddress
T
Word
Address(n)
S
T
A
R
Slave
Address
T
Data(n)
S
S
A
A
A
C
C
C
K
K
K
Figure 47. RANDOM READ
Data(n+1)
A
A
C
C
K
K
S
Data(n+x)
T
O
P
P
MS1242-E-00
- 41 -
2010/09